? semiconductor components industries, llc, 2009 november, 2009 ? rev. 2 1 publication order number: cat310/d cat310 10 channel automotive led display driver description the cat310 is a 10 ? channel led driver for automotive and other lighting applications. all led output channels are driven from a low on ? resistance open ? drain high voltage cmos nch ? fets and are fully compliant with ?load dump? transients of up to 40 volts. the led bias current of each channel can be set independently using an external series ballast resistor, making the device ideal for multi ? color instrumentation displays. a high ? speed serial interface (suitable with both 3.3 volt and 5 volt systems) feeding a 10 bit shift register is used to program the desired state (on/of f) of each channel. the device offers a blanking control pin (blank) which can be used to disable all channels on demand. a serial output data pin (sout) is provided to daisy ? chain devices in large cluster led applications. during initial power up all channels are reset and cleared via an under ? voltage lock out (uvlo) detector and for added protection all channels are disabled in the event of a battery over ? voltage condition (19 volts or more). features ? automotive ?load dump? protection (40 v) ? 10 independent led channels ? up to 50 ma output per channel ? overvoltage detection at 19 v ? serial interface for channel programming ? daisy chain output for multi ? driver cascading ? led blanking control ? operating temperature from ? 40 c to +125 c ? 20 ? pin soic package ? this device is pb ? free, halogen free/bfr free and rohs compliant applications ? automotive lighting ? white and other color high brightness leds ? multi ? color high ? brightness led cluster displays ? general led lighting http://onsemi.com soic ? 20 w suffix case 751bj pin connections nc blank vcc vbatt pgnd out5 out6 out7 out8 out9 sclk xlat sin sout gnd out4 out3 out2 out1 out0 cat310w marking diagram device package shipping ordering information cat310w soic ? 20 (pb ? free) 1,000/tape & reel cat310w = specific device code 1
cat310 http://onsemi.com 2 figure 1. typical application circuit 1 f 14 v (typical) rs10 330 rs2 rs1 30 ma 5 v sout gnd pgnd blank xlat sin sclk vbatt out0 out1 out9 cat310 v battery v cc vcc table 1. absolute maximum ratings parameter rating unit vcc voltage 7 v input voltage range (sin, sclk, blank, xlat) ? 0.3 v to vcc + 0.3 v v sout voltage range ? 0.3 v to vcc + 0.3 v v peak out0 to out9 voltage 40 v vbatt input voltage 40 v dc output current on out0 to out9 70 ma storage temperature range ? 55 to +160 c operating junction temperature range ? 40 to +150 c lead soldering temperature (10 sec.) 300 c esd rating: low voltage pins human body model machine model 3000 300 v esd rating: vbatt, out[0:9] pins human body model machine model 1000 100 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 2. recommended operating conditions parameter range unit vcc 3.0 to 5.5 v voltage applied to out0 to out9 9 to 17 v output current on out0 to out9 0 to 50 ma ambient temperature range ? 40 to +125 c
cat310 http://onsemi.com 3 electrical operating characteristics table 3. dc characteristics (vcc = 5.0 v, ? 40 c t a 125 c, over recommended operating conditions unless specified otherwise.) symbol name conditions min typ max units i stby standby quiescent current static input signal. all outputs turned off. 1 10 a v ovp vbatt over voltage protection trigger threshold 17 19 21 v v uvlo vcc under voltage lockout trigger threshold 1.7 2.5 v r sw switch on resistance for out0 to out9 i o(n) = 30 ma 2 5 12 i o(n)lkg out0 to out9 output switch leakage v (out(n)) = 15 v 0.1 10 a i xlat xlat internal pull ? down current xlat = v cc xlat = 0.3 v 4 1 10 3 30 6 a i blank blank internal pull ? up current blank = 0 v blank = v cc ? 0.3 v 4 1 10 3 30 6 a v ih v il logic high input voltage logic low input voltage 0.3 v cc 0.7 v cc v i il logic input leakage current (sclk, sin) v i = v cc or gnd ? 5 0 5 a v oh v ol sout logic high output voltage sout logic low output voltage i oh = ? 1 ma i ol = 1 ma v cc ? 0.3 v 0.3 v table 4. switching characteristics (vcc = 5.0 v, ? 40 c t a 125 c, over recommended operating conditions unless specified otherwise.) symbol name conditions min typ max units sclk f sclk sclk clock frequency 10 mhz t wh/wl sclk pulse width high or low 30 ns sin t su setup time sin to sclk 10 ns t h hold time sin to sclk 10 ns xlat t w xlat pulse width sin to sclk 20 ns t h hold time sclk to xlat 20 ns t r sout rise time (10% to 90%) c l = 15 pf 20 ns t f sout fall time (90% to 10%) c l = 15 pf 15 ns t pd propagation delay time blank to out(n) 25 ns t pd propagation delay time blank to out(n) 25 ns t pd propagation delay time sclk to sout 25 ns 1. all logic inputs contain schmitt trigger inputs.
cat310 http://onsemi.com 4 + ? + ? 10 bit data latches disable 19 v 2.5 v uvlo reset sout sclk sin xlat blank vbatt out0 out9 or 10 bit shift register 10 bit driver drv0 drv9 sw ? 0 sw ? 9 gnd pgnd figure 2. block diagram vcc
cat310 http://onsemi.com 5 pin descriptions vcc is the supply input for the internal logic and is compatible with both 3.3 v and 5 v systems. the logic is held in a reset state until vcc exceeds 2.5 v. it is recommended that a small bypass ceramic capacitor (1 f) be placed between vcc and gnd pins on the device. sin is the cmos logic pin for delivering the serial input data stream into the internal 10 ? bit shift register. the most recent or last data value in the serial stream is used to configure the state of output channel ?zero? (out0). during the initial power up sequence all contents of the shift register are reset and cleared to zero. sclk is the cmos logic pin used to clock the internal shift register. on each rising edge of clock, the serial data will advance through one stage of the shift register. xlat is the cmos logic input used to transfer data from the 10 ? bit shift register into the output channel latches. an internal pull ? down current of 10 microampere is present on this pin. when xlat is low, the state of each output channel remains unchanged. when xlat is driven high, the contents of the shift register appear at their respective output channels. an external pull ? up resistance of 10 k or less is adequate for logic high. pgnd, gnd pins should be connected to the ground on the pcb. blank is the cmos logic input (active high) used to temporarily disable all outputs. an internal pull ? up current of 10 microampere is present on this pin. the blank pin must be driven to a logic low in order for channel outputs to resume normal operation. an external pull ? down resistance of 10 k or less is adequate for logic low. sout is the cmos logic output used for daisy chain applications. the serial output data stream is fed from the last stage of the internal 10 ? bit shift register. on each rising edge of the clock, the sout value will be updated. the data value present on this pin is identical to the data value being used for configuring the state of output channel nine (out9). at initial power up, the sout data stream will contain all zeroes until the shift register has been fully loaded. vbatt input monitors the battery voltage. if an over ? voltage, above 19 v typical, is detected, all outputs are disabled. upon conclusion of the over ? voltage condition, all outputs resume normal operation. the current drawn by the vbatt pin is less than 1 microampere during normal operation. out0 ? out9 are the ten led outputs connected internally to the switch n ? channel fets. they sink currents up to 50 ma per channel and can withstand transients up to 40 v compatible with automotive ?load dump?. the output on ? resistance is 5 , and the off ? resistance is 5 m . table 5. pin table pin number pin name description/function 1 sclk clock input for the data shift register. 2 xlat control input for the data latch. 3 sin serial data input. 4 sout serial data output. 5 gnd ground. 6 ? 10 out4 ? out0 open drain outputs. 11 ? 15 out9 ? out5 open drain outputs. 16 pgnd ground for led driver outputs. 17 vbatt battery sense input. 18 vcc power supply voltage for the logic 19 blank blank input. when blank is high, all the output drivers are turned off. 20 n.c. no connect.
cat310 http://onsemi.com 6 typical characteristics ( vcc = 5 v, vbatt = 14 v, t amb = 25 c, unless otherwise specified.) figure 3. vbatt overvoltage detection amplitude between 16 v and 26 v figure 4. blank and output waveform 1 msec / div 50 sec / div led vbatt out pin led blank figure 5. xlat pull ? down current vs. input voltage figure 6. blank pull ? up current vs. input voltage xlat voltage (v) blank voltage (v) 5 4 3 2 1 0 0 2 4 6 8 10 12 14 5 4 3 2 1 0 0 2 4 6 8 10 12 14 figure 7. vbatt load dump figure 8. switch on ? resistance vs. vcc 5 msec / div vcc voltage (v) 40v vbatt 6 5 4 3 2 0 2 4 6 8 10 12 xlat current ( a) blank current ( a) switch on resistance ( ) 125 c ? 40 c 85 c 25 c 125 c ? 40 c 85 c 25 c 125 c ? 40 c 85 c 25 c vcc = 5 v 5v/div current 50ma/div voltage 10v/div 5v/div 18v current 50ma/ div 10v/div led current 20ma/ div
cat310 http://onsemi.com 7 typical characteristics ( vcc = 5 v, vbatt = 14 v, t amb = 25 c, unless otherwise specified.) figure 9. output channel leakage vs. bias voltage figure 10. quiescent current vs. temperature output pin bias voltage (v) temperature ( c) 15 14 13 16 12 11 10 0 2 4 6 8 10 12 14 100 75 125 50 25 0 ? 25 ? 50 0 5 10 15 20 figure 11. vbatt overvoltage detection vs. temperature figure 12. vcc undervoltage lockout vs. temperature temperature ( c) temperature ( c) 100 75 50 125 25 0 ? 25 ? 50 14 16 18 20 22 24 100 75 125 50 25 0 ? 25 ? 50 0 0.5 1.0 1.5 2.0 2.5 3.0 output pin leakage ( a) quiescent current ( a) overvoltage detection (v) undervoltage lockout (v) 125 c ? 40 c 85 c 25 c functional description the cat310 implements a 10 ? bit serial ? in shift register for storing the setting of the ten outputs. serial input data sin are clocked into the shift register on the rising edge of the clock. at the 10 th clock pulse, the first data bit entered is outputted from the shift register to sout. the following clock pulses will output the following data bits onto sout. the output data pattern replicates the input data stream with a delay of ten clock pulses. the 10 ? bit data pattern present in the shift register is stored in the 10 ? bit data latch when the latch signal xlat is logic high. when xlat transitions to logic low, data are latched and stay unchanged for as long as xlat remains low. the last serial input data corresponds to out0. the serial input data that was received 10 clock pulse ago is stored in out9. when the blank input is logic high, all the output switches are in the off state. if the blank input is low, the 10 ? bit data latches control the 10 output switches. a data bit value of zero keeps the switch off. a data bit value of one keeps the switch on. serial to parallel shift register clk sin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 sout data latch xlat led out0 led out1 led out2 led out3 led out4 led out5 led out6 led out7 led out8 led out9
cat310 http://onsemi.com 8 figure 13. timing diagram sclk sin sout xlat blank outn output switch off output switch on t pd t h t su t wl t wh 1/f sclk t h t su t pd t pd application information for applications with a large number of leds, several cat310 drivers can be daisy chained. the serial data output pin (sout) of the first driver is connected to the second driver data input pin (sin). this sequence is repeated until the last driver is linked. all drivers are controlled by the same clock signal. figure 14 shows an example with three cat310 devices driving a total of 30 leds in parallel. the controller transmits the serial data sequentially through the cat310 devices. for n drivers connected in cascade, after 10 x n clock pulses, the data are latched with one single xlat transition. figure 14. daisy chain application diagram 4.7 f 5 v blank xlat sout gnd pgnd vcc vbat out0 out1 out9 cat310 controller sclk sin v cc v batt v battery = 14 v (typical) v cc v cc + ? + ? blank xlat sout vcc vbat out0 out1 out9 cat310 sclk sin blank xlat sout vcc vbat out0 out1 out9 cat310 sclk sin gnd pgnd gnd pgnd
cat310 http://onsemi.com 9 package dimensions soic ? 20, 300 mils case 751bj ? 01 issue o a2 e1 e a1 e pin#1 identification b d c a top view side view end view 1 1 h h l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-013. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.31 0.20 0.25 12.60 10.01 7.40 1.27 bsc 2.64 0.30 0.51 0.33 0.75 13.00 10.64 7.60 l 0.40 1.27 2.36 12.80 10.30 7.50 0.41 0.27 0.81 a2 2.05 2.55 2.49 1 5o 15o
cat310 http://onsemi.com 10 example of ordering information (note 2) prefix device # suffix company id cat 310 product number 310 ? t1 t: tape & reel 1: 1,000 / reel tape & reel (note 5) (optional) w package w: soic 2. the device used in the above example is a cat310w ? t1 (soic, tape & reel, 1,000 / reel). 3. all packages are rohs ? compliant (lead ? free, halogen ? free). 4. the standard lead finish is matte ? tin. 5. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat310/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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